A silicide is a compound that combines silicon with (usually) more electropositive elements (e.g., nickel (Ni) or cobalt (Co)). The term “silicide” refers to a technology used in the microelectronics industry to facilitate low resistance (enhanced ohmic) electrical contacts between the active regions of a semiconductor device (e.g., a source or drain diffusion formed in a silicon substrate) and a supporting interconnect (e.g., aluminum or other metal) structure. The silicide formation process involves the reaction of a thin film containing metal with the surface of a silicon structure over the active regions of the device, ultimately forming a metal silicide contact through a series of annealing processes. The term “salicide” is a compaction of the phrase self-aligned silicide. The description “self-aligned” suggests that the contact formation does not require lithographic patterning processes, as opposed to a non-aligned technology such as polycide. Note that the terms “silicide” and “salicide” are effectively interchange as used herein because the metal silicide structures formed by the described formation processes may be accurately referred to as salicide.
Cobalt silicide (CoSi) and nickel monosilicide (herein “NiSi” or “NiSi silicide”) are two silicide materials that are widely used in the microelectronics industry, with CoSi typically used in older fabrication technologies having larger minimum feature sizes (e.g., 0.13 μm and larger), and NiSi being the most commonly used silicide in VLSI technologies such as SOI or deeply scaled down CMOS (e.g., having minimum features sizes below 0.09 μm). NiSi silicide provides advantages over CoSi due to its smaller silicon consumption during the silicidation (silicide formation) process, due to its lower processing/formation temperature and thermal budget, due to its absence of the bridging failures, and due to its ability to produce small resistance increases in narrow silicided polysilicon lines. In addition, CoSi consumes substantially more silicon during its formation (i.e., 3.6 nm for 1 nm of metal vs. 1.8 nm for NiSi), which this makes the use of CoSi in transistors fabricated on SOI wafers with thin (0.18 micron and below) device layers difficult.
During early stages of the NiSi silicidation process, nickel reacts with silicon during the sputtered nickel thermal processing (i.e., when the interface between the nickel and silicon is heated to a temperature of approximately 300° C.) to form initial phases of nickel silicide. The resistivity of the initial nickel silicide phase decreases when Rapid Thermal Processing (RTP) is subsequently performed at temperatures between 400° C. and 550° C., which causes the initial metal-rich phases to convert into the desired nickel monosilicide (NiSi). The main disadvantage of NiSi formed in this manner is its relatively low thermal stability—that is, the low-resistivity NiSi transforms into high-resistivity NiSi2 if heated above 600° C. The increased resistivity is associated with enhanced diffusion of Ni atoms, which are released during the conversion of NiSi to NiSi2, into the underlying silicon structure, which creates generation-recombination centers that cause excessive leakage currents in the Si—NiSi interface junctions (see, e.g., M. Tsuchiaki et al., “Junction Leakage Generation by NiSi Thermal Instability Characterized Using Damage-Free n+/p Silicon Diodes”, Jpn. J. Appl. Phys. 43 5166, 2004 (Toshiba)).
The release of free Ni atoms due to overheating is not the only player leading to enhanced diode leakages. A certain level of hydrogenation is needed to decrease the sheet resistance of the silicide films at the expected processing temperatures [see A. Vengurlekar et al., “Influence of hydrogen plasma surface treatment of Si substrate on Nickel Silicide formation” Journal of Vacuum Science & Technology. B, May 2006 (Freescale)]. However, excess hydrogen was shown to lead to defects at Si—NiSi interface junction. The above mentioned destruction of the NiSi phase and the Ni-enhanced penetration into silicon starts at temperatures of approximately 500° C. for specimens with hydrogen-related defects. Ni-enhanced diffusion causes not only the uniform leakage increase due to appearance of the recombination centers, but also stimulates Ni/NiSi spikes in the silicon. These spikes can reach the metallurgical junctions and result in catastrophic failures (junction breakdowns) of the silicided diodes.
Another possible mechanism that leads to the silicided diode failures is connected with dislocations and cracking in the silicon structure under the NiSi. The as-deposited NiSi induces small mechanical stresses in the Si-substrate [see A. Steegen and K. Maex, “Silicide-induced stress in Si: origin and consequences for MOS technologies,” Materials Science and Engineering: R: Reports, vol. 38, no. 1, pp. 1-53, 2002], and significant additional mechanical stresses may be introduced by subsequent processing. When the local shear stress exceeds the critical yield stress of silicon (e.g., due to thermal expansion at elevated temperatures), dislocations may be generated in the Si-substrate underneath silicide lines.
The stress-related dislocation phenomena mentioned above become especially important when special stressing structures are utilized to enhance channel electron mobility in MOS transistors formed by SOI or CMOS technology. Conventional stressing structures (also referred to as “stressing layers”, “stress liners” or “stressors”) are single-layer dielectric structures disposed over associated transistors (e.g., NMOS or PMOS transistors formed using SOI or deeply scaled down CMOS technologies), where the stressing structures are specifically formed with a residual mechanical (tensile or compressive) stress that serves to significantly increase carrier mobility in the associated transistor's channel region by applying transmitting stress into the underlying silicon. Conventional stressing structures comprise silicon carbide, silicon nitride or silicon oxynitride, and are typically deposited using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure CVD (LPCVD) processes. For example, U.S. Pat. No. 7,084,061 Mil Chun Sul “Methods of fabricating a semiconductor device having MOS transistor with strained channel” (2006, Samsung) describes forming NiSi structures on the gate electrode and the source and drain regions of an NMOS transistor, forming a stressing layer on the NiSi layer over the gate electrode and the source and drain regions and, after forming the stress layer, annealing the stressing layer to increase its residual tensile stress, whereby the residual tensile stress of the stressing layer is transmitted into the underlying silicon substrate, producing a localized tensile stress component in the channel region separating the active regions of the transistor.
A problem with the formation of stressing layers on NiSi silicide using conventional methods is that the stressing layer deposition process can result in various parasitic effects (e.g., poor adhesion and pealing) due to the presence of excessive oxygen and hydrogen at the interface between the stressing layer and the NiSi silicide. For example, when a natural oxide film is left at the interface between the NiSi and a silicon nitride (SiN) stressing layer, subsequent process steps (e.g., heating the semiconductor substrate after deposition of the SiN layer) may result in abnormal changes of the NiSi structure. Oxygen in the native oxide film on the NiSi surface (or on a capping TiN layer) was reported to be a cause of poor adhesion of the overlying SiN layer. The silicon nitride film, especially a rather thick stressing layer at the surface of NiSi, may peel off or blister from the silicide. Such blistering and peel-off can lead to NiSi and Si defects and thus to leakages in diodes under NiSi. The mechanism of such defects creation could be connected with exceeding the threshold for defect generation stresses and also with changes of NiSi structure during subsequent thermal processing.
Various approaches have been developed to improve the adhesion between SiN and NiSi. For example, U.S. Pat. No. 6,831,008 (“Nickel silicide-silicon nitride adhesion through surface passivation”, Jiong-Ping Lu, Texas Instruments, 2004) associates the adhesion problems with a silicon-rich film formed in the beginning of the SiN deposition, and describes treating the NiSi surface covered with TiN capping layer with plasma-activated nitrogen species for better adhesion to silicon nitride. Treatment of NiSi surfaces in an inert gas has also been taught as improving adhesion between SiN and NiSi. For example, U.S. Pat. No. 7,923,319 (“Method for manufacturing a semiconductor integrated circuit device circuit device”, T. Futase, Renesas, 2011) teaches a low bias plasma treatment in an inert gas atmosphere before SiN deposition, but in this case the SiN film does not include an intentionally formed residual stress (i.e., the SiN film serves as a contact etch stop layer (CESL), not as a stressor). Japanese Patent No. JP 200031092 teaches irradiating NiSi with hydrogen active species (H*) in order to remove the oxide without causing NiSi agglomeration at the subsequent thermal steps.
Hydrogen as a cause of the interface defects between SiN and silicon is mentioned in “Lifting Defect Improvement of Plasma Enhanced Nitride”, Hyunkwan Yu, 2014 ECS—The Electrochemical Society. Hydrogen radicals were generated during a plasma nitride deposition process, and these hydrogen radicals could be captured between SiN and silicon, which caused lifting defects. It is worth mentioning here once again that alternative mechanisms are suggested, but it has been confirmed by research groups from several leading semiconductor companies that the excess hydrogen can generate hydrogen related surface effects and diode failures.
A method for fabricating a semiconductor device having low hydrogen contents is taught in U.S. Pat. No. 6,071,784 (Mehta et al., 2000), which teaches an etch stop silicon nitride layer deposited on a semiconductor substrate after silicidation, and then heated to approximately 750° C. to decrease the hydrogen content and stabilize MOS transistors by finding the necessary hydrogen balance. Unfortunately, this method is not suitable for NiSi because, as mentioned above, the high temperature heat treatment would cause the low resistance NiSi phase to transformation into a high resistance NiSi2 phase.
Other methods were also attempted by various groups to optimize the performance of NiSi and overlying layers: moderation of post-Ni silicidation thermal budget, alloying Ni with Pt, addition of metals such as Zirconium to TiN capping layer, and others. Nevertheless, a problem of integrating NiSi with SiN cap layers, and in particular thick SiN stress liners, still exists in the microelectronics (semiconductor fabrication) industry.
What is needed is a method for addressing the various problems mentioned above related to the formation of stressing structures on NiSi structures. In particular, what is needed is an improved NMOS device that utilizes a stressing structure to enhance the mobility of channel electrons, and avoids the various problems mentioned above related to the formation of the stressing structure on the NMOS device's NiSi structures.